1. Field of the Invention
The invention relates in general to a non-volatile memory (NVM) device, and more particular, to a structure, a fabrication method and an operation method of a flash memory device.
2. Related Art of the Invention
Having the functions of performing multiple times of saving, reading and erasing operations and retention of saved data even when the power Is interrupted, flash memory has become a non-volatile memory device broadly applied in personal computer and electronic equipment.
The typical flash memory uses doped polysilicon to form the floating gate and the control gate. While performing a program or erase operation, the source region, the drain region and the control gate are biased with suitable voltages, such that electrons are injected into or pulled from the polysilicon floating gate.
Generally speaking, the electron injection of the flash memory includes a channel hot-electron injection (CHEI) mode and Fowler-Nordheim (F-N) tunneling mode. The program and erase operation modes of the device are varied according to the methods of electron injection and pull-away.
The NOR array is the most commonly seen flash memory array. In the NOR array, every two memory cells share the contact window of a bit line and a common source line. Therefore, each memory cell occupies the dimension of half of a contact window and half line width of a source line. As each memory cell Is directly connected to the bit line, the memory cell of the NOR array can arbitrarily perform reading and writing operations. The relatively low serial resistance allows a larger current during reading operation of the memory cell; and therefore, the reading speed is faster. However, in the NOR array, a contact window has to be formed in the drain region every two memory cells, so that a larger space is occupied by each memory cell. It is thus difficult to enhance the device integration.
The present invention provides a structure, a fabrication method and an operation method of a flash memory device with enhanced device integration.
The structure of the flash memory device provided by the present invention includes the following. A second conductive type first well is formed in a first conductive type substrate. A first conductive type second well is formed in the second conductive type first well. A stacked gate structure is formed on the first conductive type substrate. A first conductive type source region and a first conductive type drain region are formed in the first conductive type second well at two respective sides of the stacked gate structure. The first conductive type drain region and the first conductive type second well are electrically connected to each other. A second conductive type third well is formed in the first conductive type second well, and the second conductive type third well encompasses the first conductive type source region and extends through underneath the stacked gate structure towards the first conductive type drain region. A contact window is formed across the junction between the first conductive type source region and the second conductive type third well to short circuit these two regions.
In the present invention, an N-well is formed in a deep P-well. The N-well and the N-type drain region are electrically connected as a buried bit line. Therefore, an additional contact window is not required to connect between the bit line and the N-type drain region. The integration is thus enhanced. According to the above structure, the flash memory can use FN tunneling effect to inject electrons from the drain region to the floating gate for programming, and the channel FN tunneling effect for performing an erase operation. In addition, as the P-well is short circuited with the source region, the potential of the P-well is the same as that of the source region, such that the isolated P-well has a potential.
The present invention provides a method for fabricating a flash memory device. A substrate on which a second conductive type first well, a first conductive type second well and a stacked gate structure have been sequentially formed is provided. A first patterned photoresist layer is formed on the substrate. The photoresist layer exposes a portion of the substrate predetermined for forming a source region. An ion implantation step is performed to form a second conductive type third well in the first conductive type second well at the part predetermined for forming the source region. The second conductive type third well extends from the part predetermined for forming the source region underneath the stacked gate to an area predetermined for forming a drain region. The first photoresist layer is removed, and a second patterned photoresist layer exposing the area predetermined for forming the drain region is formed. An ion implantation step is performed to form the drain region in the first conductive type second well at the area predetermined for forming the drain region. The drain region is electrically connected to the first conductive type second well. The second photoresist layer is removed, and a third patterned photoresist layer, is formed exposing the substrate predetermined for forming the source region. An ion implantation step is performed for forming the source region in the second conductive type third well in the area predetermined for forming the source region. A spacer is formed at a sidewall of the stacked gate structure. A fourth patterned photoresist layer is formed exposing the source region. The fourth patterned photoresist layer and the spacer are used as a mask for etching the substrate at the source region until reaching the junction between the source region and the second conductive type third well. After removing the fourth photoresist layer, a contact window is formed on the source region. The contact window short circuits the source region and the second conductive type third well.
In the present invention, the photoresist layer is formed covering the area predetermined for forming the drain region first. The area predetermined for forming the source region is implanted with P-type dopant. A thermal process is then performed to drive in the P-type dopant to form a P-well. The P-well extends from the source region through the portion of the substrate underneath the stacked gate to reach the drain region. Another patterned photoresist layer is formed to cover the predetermined source region. Arsenic and phosphoric ions are implanted to form an N-type drain region. Arsenic ions are then implanted to form the N-type source region. The N-type drain region doped with phosphoric ions can withstand high voltage, while the arsenic ions reduce the resistance of the N-type drain region. As the N-type drain region and the N-well are electrically connected and the N-well is used as the buried bit line, an additional contact window electrically connecting the bit line the N-type drain region is not required. Therefore, the device integration is enhanced.
The present invention further provides an operation method of a flash memory device. The flash memory device includes an N-type substrate, a first P-well in the N-type substrate, an N-well in the first P-well, a stacked gate structure including a control gate on the substrate, a source region and a drain region in the N-well at two respective sides of the stacked gate structure, and a second P-well in the N-well. The source region and the drain region are N-type conductive. The drain region is electrically connected to the N-well. The second P-well encompasses the source region and extends under the stacked gate structure to the drain region. The operation method includes the following steps. While programming the flash memory, a first negative voltage is applied to the control gate, such that the source region is floated. A first positive voltage is applied to the drain region for programming the flash memory according to FN tunneling effect. While performing an erase operation on the flash memory, a second positive voltage is applied to the control gate, such that the drain region is floated. A second negative voltage is applied to the source region to use channel FN tunneling effect to perform an erase operation on the flash memory device.
Since the program operation is performed according to the FN tunneling effect, the electron injection efficiency is high, so that the memory current for programming the memory cells is decreased, and the operation speed is increased. As the program and erase are both performed according to F-N tunneling effect, the current consumption is reduced, and the power consumption for the whole memory device is consequently reduced.
The present invention further provides a flash memory array comprising a plurality of memory cells, a plurality of word lines, a plurality of buried bit lines and a plurality of source lines. Every two of the memory cells forms a set. The memory cell sets are arranged into a column/row array. The memory cells in each set share a common source region and a contact window. The neighboring sets share a common drain region. The drain region of each memory cell of each set in each row is coupled to a corresponding buried bit line, and the source region of each memory cell of each set in each row is coupled to a corresponding source line via the common contact window. The gate of each memory cell in each column is coupled to a corresponding word line.
In the present invention, the memory cell array uses a buried bit line to couple with the drain region of the memory cells in each row without an additional contact window for electrically connecting the bit line and the N-type drain region. Therefore, the device integration is enhanced. Further, as the buried bit line is an N-well located alongside of the drain region, the current is not affected even if the resistance of the N-well is high, so that the operation speed will not be affected either. In the memory cell array of the present invention, a buried bit line can connect 32 to 64 memory cells in series, and a contact window is used to connect the buried bit line and a metal line. Therefore, compared to the conventional NAND memory array, the memory cell array provided by the present invention has a relatively high integration.